What is Register-transfer-level (RTL) Design?

Register-transfer-level (RTL) design is an essential step in the design process of digital circuits. It defines and optimizes the logical functionality of a digital design at an abstract level before specifying the circuit's physical layout. Engineers convert the high-level desired behavior of their design to software code using a hardware description language (HDL) like VHDL or Verilog. 

The first HDLs capable of modeling at the RTL level were developed in the 1980s, and evolved into full-design systems that enable engineers to model the data flow in electronic circuits. 

As designs became larger and more complex and manufacturing technology enabled new ways of carrying out logical and mathematical operations, RTL design methods kept pace. Over time RTL design became a required step in the digital design process that bridges the system specification and the circuit design steps. 

The abstract nature of the RTL description allows for quick studies and fast design iterations to obtain an acceptable and optimized design before delving into the more complex and time-consuming phases of the design process.

RTL design is a key part of the integrated circuit design cycle that enables engineers to optimize their designs at the register, operator, and data flow stages before they need to start worrying about the physical components and how they’re connected. In this article, we’ll cover some fundamentals, describe where RTL design fits into the design of digital circuits, and explain the RTL design flow. We’ll then show how RTL design fits into field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) chip design and reveal what the future of RTL design looks like.

The phrase “register-transfer” refers to how the language describes the data flow between registers and how to apply logical operations and mathematical operations to the data. Engineers use RTL design to describe functional blocks, so as to define the behavior of a discrete component used to execute a specific function. Each functional block has a description of the registers in the block, referred to as the sequential circuit, and a combinational circuit that contains the logical operation for the functional block. They also use the HDL to describe how functional blocks are connected to define the flow of data through the circuit.

The power of RTL design is how it takes a complex system and breaks it up into relatively simple blocks represented by HDL code. Here are a few fundamentals that are important in understanding how RTL design is used.

Registers

In RTL design, a hardware element that can store a set amount of data is called a register. They are usually implemented as D flip-flops. The value of a register can be read as input to a logical operation, or it can be set as the output of an operation. Characterizing how data flows between registers and how the data is changed by an operation is the fundamental purpose of RTL design.

Hardware Description Language (HDL)

The most important part of RTL design is the code that describes the behavior of the circuit. An HDL is a specification language that looks a lot like a programming language, with variables, function calls, logical statements like if-then-else and CASE, Boolean statements, and math. However, HDLs are specifically designed to describe the behavior and structure of electronic circuits, usually integrated circuits. One thing that sets HDL apart from programming languages is that the concept of time is included within the language so that operations can be triggered by clocks in the circuit.  

This is accomplished through the use of a variable defining the value of the digital clock in the circuit, as in this VHDL simple example of an inverter where the output (Q) is set to the input value (D) when the clock value, clk, goes from a low to a high state (rising edge):

D <= not Q;

process(clk)
begin
    if rising_edge(clk) then
        Q <= D;
    end if;
end process;

The most commonly used HDL, Very High-Speed Integrated Circuit Hardware Description Language (VHDL), is a verbose, strongly typed language with a syntax that doesn’t look like the C language. It’s the preferred HDL for describing more complex system designs. 

Another common HDL is Verilog or its superset, SystemVerilog. It is more concise, weakly typed, and flexible, and its syntax looks like C code. Because it’s easy to learn and create descriptions in, engineers prefer it when starting out or when their circuits are not as complicated. IEEE defines both Verilog and VHDL as industry standards. 

Here’s a simple example of an AND gate in both languages. An AND gate has two inputs and one output. If the inputs are both equal to 1, the output is 1. If they are not equal or if both are set to 0, the output is 0. 

VHDL describes an AND gate as: 

entity my_and is -- First, you define the entity
  port (
     inp1: in  std_logic; -- The first port
     inp2: in  std_logic; -- The second port
     rst: out std_logic   -- The output port
  );
end my_and;

architecture blk of my_and is -- Next, define the architecture
begin
  process(inp1, inp2) -- With the inputs, do the following
  Begin
    -- Use a simple if-then-else statement
    if((inp1=’1’) and inp1=’1’))then
      rst <= ’1’;
    else
      rst <= ’0’;
    End if;
  end process
end blk;

The Verilog for the AND gate looks like this:

module my_and(inp1,inp2,rst); // define the module call
input inp1, inp2;             // define inputs and output
output rst;

assign rst = inp1 & inp2;    // use the & (and) operator

endmodule

The logic takes the value at the two input ports and sets the output to 1 if both ports are 1. This is a simple example, but this type of code can represent every entity in the system and can then be combined to define an entire digital circuit. Typical basic building blocks include adders, multipliers, counters, memory, and state machines. Once the design engineer defines the system, the code is sent to a compiler. If it compiles with no errors, the engineer can use the result to test their system.

Logical Operations

There are two types of operations in RTL design. The first, logical operations, perform bitwise evaluation and modification of the data stored in registers. Logical operations like AND, OR, NOT, XOR, and shift are created by defining the logical behavior in the HDL. The example above shows how an AND can be represented in VHDL and Verilog. Logical operations represent logic gates in the hardware. 

Arithmetic Operations

The second type of operations in RTL design are arithmetic operations. They take the data in registers and add, subtract, multiply, and divide. They are represented in the HDL with standard mathematical operators. As an example, adding two numbers in VHDL would use the line:

rst <= inp1 + inp2;

— where inp1 and inp2 are two input registers, and rst is assigned to the output register. Arithmetic operations in RTL represent dedicated physical elements such as adders, subtractors, multipliers, and dividers. 

Synchronous and Asynchronous Actions

The RTL design can represent the flow of data in either a synchronous or an asynchronous manner. For synchronous, a routine is executed, or triggered, by the system clock input to the function. For asynchronous, the routine is executed when a value of one or more input ports changes in a specific way. This is implemented by checking the input values of the clock input or the non-clock inputs to see if they have changed with an if-statement. 

The modern integrated circuit (IC) design flow involves taking a specification for what the device needs to do and turning it into a packaged semiconductor chip. The level of abstraction that RTL design delivers enables engineers to concentrate on the system's higher-level functions without the need to consider the particulars of how to physically implement the design. 

The first step in an IC design flow is to define the system specifications and the architectural design. This information is converted into HDL code. Engineers then use that code to define the functional and logical design. Once that is completed, the design is converted into a netlist, which is then used to create the circuit design, followed by the rest of the design process. 

The abstract representation using RTL design is done as early in the design process as possible — before time and money are spent on the physical design, verification of the physical design, or actual fabrication of hardware. Fitting the RTL design step into the process requires good integration between the system specification at the start and strong tools that convert the registers, operations, and data flow into an actual circuit when the RTL design is done. 

The goal of the RTL design flow is to define and optimize the functionality of an integrated circuit, usually an FPGA or ASIC device. Design engineers use the RTL design flow to first define the logic and flow of the device to test and optimize the system, then convert the RTL definition to a netlist. The following five steps define the typical RTL design methodology.

1. High-level Synthesis 

The first task in the flow is to convert the specifications for the device into HDL code with as few edits as possible. In most cases, engineers represent the desired behavior of the device in a standard programming language like C or C++. A software tool then breaks down the algorithms in the software model into the chosen specification language. This step can be skipped for simpler designs, but for more complex designs it can save a considerable amount of effort. 

2. RTL Coding

Engineers then create or refine the code. Designers get into the details of specific registers, the operations they need, and how the data flows. One important part of this step is the use of modules to describe common operations and specific parts of the system. Once a module is created, it can be reused where applicable, greatly simplifying the complexity of the overall design. 

3. Optimization of Performance, Power, and Area (PPA)

Once the coding is completed, the optimization process begins. The goal of this step is to improve performance, minimize power usage, and reduce the physical size of the design. 

Timing and Logic Simulation

Simulation tools are used to conduct timing analysis and track register values throughout the system. The design is checked at the register-transfer level to ensure there are no timing issues across the circuit and that the operations produce the expected outputs. This is where the design team works to debug any issues, including power glitches, in the system as early as possible in the design process. 

Power Estimation

Each device in the system consumes some amount of power, and design engineers need to know how much power is being consumed and iterate on their design to understand power distribution and minimize power consumption. Ansys PowerArtist™ software is used by many leading semiconductor design companies to analyze, profile, and reduce power at the register-transfer level. It delivers a fast turnaround that enables design teams to slice and dice power, identify power-inefficient RTL code, and tag every wasted toggle in the design. 

Area Minimization

Every component in an integrated circuit takes up physical space, as does the routing between those components. Although the RTL design process doesn’t look at the physical size of components, it does capture how many components there are and the complexity of the connections between them.

4. Verification

Once the design has been optimized, it must be verified to make sure the specifications are all being met. It’s a critical part of the design process, and all design requirements must be checked before the design can move forward. This is done either with RTL simulation or formal verification. 

RTL simulation: Various software tools are used to dynamically verify the design. Input vectors are applied, and the resulting output vectors are compared to the expected results. The inputs and outputs are usually represented as waveforms so that the design engineer can visually inspect the system's behavior. 

Formal verification: This is a static verification process that uses automation to convert a set of behavior expectations into mathematical algorithms that explore the entire operating space of the system. The results are then mathematically evaluated to verify correctness. 

5. RTL Synthesis

Once the system’s design has been fully verified, RTL synthesis is used to convert the HDL code representation of the RTL design into a gate-level netlist. This is the front end for tools that convert the resulting schematic into a physical layout in an electronic design automation (EDA) tool. Companies like Synopsys have built a variety of synthesis tools into EDA platforms. 

Integrated circuits can be divided into two classes. Application-specific integrated circuits (ASICs) are custom designed for specific applications or tasks. Once built, the logic in the chip cannot be changed. Examples of ASIC chips are memory modules, digital voice recorders, optimized signal processors, microprocessors, central processing units (CPUs), or even something as complex as a system on a chip that includes I/O, CPU, memory, and more. 

Field-programmable gate array (FPGA) chips are semiconductor chips that can be reprogrammed after they’re manufactured. Instead of the logic being built into the geometry in the chip, FPGAs have arrays of logical blocks connected by a connection grid that can also be programmed. 

RTL design plays the same role in the first part of both design flows. Once the RTL synthesis is completed, the ASIC design flow requires engineers to plan and lay out the physical circuits, which is called floorplanning. In an FPGA design, the RTL code is converted directly into a netlist that knows what logical blocks are available and configures those blocks in the place and route step. 

The use of hardware description languages to represent the desired behavior of digital systems started in the 1970s and 1980s. It found significant favor as very large-scale integration (VLSI) grew in popularity and has kept pace with further developments in IC design. As feature size in integrated circuits continues to shrink, clock speeds continue to increase, and more functionality is packed into one chip, design engineers are presented with increasing challenges. 

Design complexity has not slowed down, and RTL tools continue to rise to these challenges. The companies developing the tool suites that designers will use to define the next generation of integrated circuits will focus on a couple of key areas to improve the ease of use, capability, and functionality of the RTL design flow. Some areas of focus are:

• Power Reduction

  Power management continues to be one of the biggest challenges across the entire integrated circuit design process, and RTL optimization continues to be the optimal place to understand and manage the voltage drops that consume power in a system. Enhancements to tools like PowerArtist software that bring more options, greater visibility, and increased speed will help teams meet this challenge.

• Seamless Integration Between Tools

  As the number of tools available for design, simulation, verification, and signoff increases, the capabilities of the existing tools will also increase. Companies providing these tools and industry organizations like IEEE will need to keep pace by updating and improving standards and providing tools that can make the flow between applications as seamless as possible.

• Inclusion of AI in the Design Flow

  Many tools used in the integrated circuit design process have used forms of machine learning (ML) and expert systems to speed process steps, especially in the layout of the physical circuits. This will only continue with improved ML algorithms and the use of generative artificial intelligence (AI) tools to suggest the most probable next steps or solutions to problems.

• Improvements to High-level Synthesis

  Vendors in the RTL space are working hard to improve the ability of engineers to convert their high-level system specification to high-level hardware languages with greater speed, and with designs that are closer to the optimal configuration.

• Smarter RTL Synthesis

  There’s room for significant gains in productivity and optimization when the gates in an RTL description are converted into actual transistors in the RTL synthesis step. As physical geometry enters the design, there’s an opportunity to make informed decisions that will simplify the downstream processes of laying out the circuit.

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