Ansys Exalto is a powerful post-LVS RLCk extraction software solution that enables IC design engineers to accurately predict electromagnetic coupling effects during the signoff phase.
Ansys Exalto is a post-LVS RLCk extraction software solution that enables IC designers to accurately capture unknown crosstalk among different blocks in the design hierarchy by extracting lumped-element parasitics and generating an accurate model for electrical, magnetic and substrate coupling. Exalto interfaces with most LVS tools and can complement the RC extraction tool of your choice.
Ansys Exalto post-LVS RLCk extraction lets IC designers accurately predict electromagnetic and substrate coupling effects for signoff on circuits that were previously "too big to analyze.” The extracted models are back-annotated to the schematic or netlist, and support all circuit simulators.
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Large complex circuits that were previously “too big to analyze” are now within reach with Exalto’s high-speed and high-capacity EM modelling for silicon devices.
The proliferation of RF and high-speed circuits in modern silicon systems has raised electromagnetic coupling to a first order effect that must be accurately modeled to reliably achieve silicon success. But generating accurate parasitic models suitable for electromagnetic coupling analysis is far more complex than traditional RC extraction. And the size of these EM models has posed a challenge for simulators.
Exalto’s unprecedented capacity enables you to analyze extremely complex layouts with ease. Its unique netlist reduction methodology makes the output netlist extremely compact, mitigating any simulation issues. This makes it possible to thoroughly analyze complex EM interactions that were previously avoided through expensive over-design and guardbanding. The result is a smaller, cheaper design with more reliable performance characteristics.
Exalto enhances existing design flows by complementing regular extractor tools and interfacing seamlessly with all LVS tools.
Ansys Exalto captures unknown crosstalk between nets and hierarchical blocks by extracting lumped-element parasitics and generating an accurate model for electrical, magnetic and substrate coupling. Exalto can model crosstalk between different hierarchy levels and run multiple “what-if” scenarios without changing your schematic. Complex coupling within sensitive RF circuitry with large digital busses/control signals are easily captured using the “point-and-click” interface. A unique netlist reduction methodology reduces the output netlist by over 90%. Exalto interfaces with all LVS tools and complements RC extractors with S-parameters and RLCk parasitics that are back-annotated for partial or complete designs.
Extract lumped-element parasitics and generate accurate models for electrical, magnetic and substrate coupling for large complex silicon circuits
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