Ansys VeloceRF is an inductive device synthesis and modeling tool that supports advanced nodes as low as 3nm and integrates with leading EDA platforms.
Ansys VeloceRF shortens the design cycle by greatly reducing the time it takes to synthesize and model complex spiral devices and T-lines. It takes only a few seconds to compile an inductor or transformer geometry, and just a couple of minutes to model and analyze it. It integrates with leading EDA platforms, instantiating ready-to-tape-out layouts.
Ansys VeloceRF allows you to synthesize devices with tight packing of multiple devices and lines for an optimized silicon floorplan. Analysis of the coupling among any number of inductive devices before detailed layout will reduce design size and reduce or eliminate guard rings.
Ansys VeloceRF shortens the design cycle by greatly reducing the time it takes to synthesize and model complex spiral devices and T-lines.
Inductor size as well as inductor-to-inductor crosstalk can impact the die size. Ansys VeloceRF helps you design smaller devices through the use of optimization criteria and geometry constraints. In addition, it calculates coupling among any number of inductors to better optimize silicon real estate and to optimize inductors in circuit context. Ansys VeloceRF’s parametric sweep support delivers an optimal performance solution in circuit context. The foundry-verified accuracy mitigates risk in your design with silicon-proven models that help eliminate crosstalk failures.
Ansys VeloceRF currently supports over 200 unique foundry processes and works with any process down to 3nm including CMOS, BiCMOS, GaAs, SOS and SOI from all semiconductor foundries - TSMC, UMC, Global Foundries, TowerJazz and Samsung, among others. The tool integrates with leading EDA design platforms and with any LVS tool.
Ansys VeloceRF synthesizes and analyzes mm-wave spiral devices and T-lines in just a few minutes. It generates DRC/DFM clean devices - including fill - down to 3nm. The devices are modeled by passive, causal S-parameters and highly compact RLCk netlist models and can be delivered as PCells/PyCells for maximum geometric flexibility. In-context optimization allows significant die size reductions through tight floor plan packing of multiple devices and lines and the reduction or elimination of guard rings. It supports high frequency with a pre-defined library of device building blocks and supports coupling among any number of inductive devices.
VeloceRF delivers comprehensive synthesis, modeling, analysis and optimization of inductive devices on silicon.
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