Ansys Totem is the proven, trusted industry leader for power noise and reliability signoff for analog and mixed-signal designs built on cloud-native elastic compute infrastructure.
Ansys Totem is the industry’s trusted gold standard voltage drop and electromigration multiphysics sign-off solution for transistor-level and mixed-signal designs. It is certified by all major foundries for finFET nodes down to 3nm with a track record of thousands of tapeouts. Totem-SC is cloud-native version of Totem based on SeaScape that gives it ultra-high speed and capacity to handle even the largest full-chip analyses.
Ansys Totem and Totem-SC are transistor-level power noise and reliability analysis platforms for analog mixed-signal IP and full custom designs. They creates IP models for SOC-level power integrity signoff with RedHawk-SC and generate compact chip models of power delivery networks for the chip and system-level.
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Signoff analysis reduces project risk by avoiding costly errors in silicon. Accurate multiphysics simulation improves design performance by eliminating wasteful margin with better silicon correlation.
Totem’s trusted multiphysics signoff analysis is a powerful way to reduce project and technology risk. Its algorithms are certified accurate by all major foundries for all finFET processes down to 3nm and are proven in thousands of tapeouts.
Totem-SC is based on the cloud-native SeaScape™ architecture for full-chip power analyses of ultra-large designs. Totem-SC enlists thousands of CPU cores with modest memory requirements to deliver fast results with same accuracy as Totem.
Totem’s advanced reliability analyses - like thermal-aware EM and statistical EM budgeting - improve safety of automotive designs. Totem also provides value at all stages from early IC prototyping stages all the way to system level. Early analysis enables cheaper and more impactful optimizations than are possible at signoff. The foundry certified silicon correlated simulation results give designers the confidence they need to achieve higher performance and lower power by avoiding wasteful and expensive overdesign.
Ansys Totem is a transistor-level power noise and reliability analysis platform for comprehensive power integrity analysis on analog mixed-signal IP and full custom designs. Totem can create IP models for SoC-level signoff using RedHawk-SC. Totem analyses span early prototype to signoff and can handle a variety of design styles such as SerDes, data converters, power management IC, embedded memories, DRAM, Flash, FPGA, and image sensors. It analyses substrate noise, RDSON, self-heat, and ESD (with Ansys PathFinder™). Totem-SC’s cloud-native elastic compute architecture has the capacity to handle very large designs with modest memory overhead.
Ansys Totem and Totem-SC set the standard for analog mixed-signal signoff
•Early prototyping
•Several million xtor flat
•Cloud processing with Totem-SC
•Incremental and What-If analysis
•Digital and analog simulated together
•Vector or vectorless activity
•Built-in PG network extraction
Ansys Totem/Totem-SC offer capabilities like power grid weakness analysis, missing vias, P2P checks and variety of early-stage static and dynamic IR and EM analysis that can highlight design weakness in early design stages before it is LVS clean. These allow designers to decide on power grid planning, bump placement, decoupling cap optimization, EM on critical nets, etc.
Ansys Totem/Totem-SC accurately sign off large, mixed-signal designs. Key features like native handling of the place and route digital database and hierarchical analysis of complex AMS simplifies the overall flow with a bottom-up validation of each block and a comprehensive multi-state transistor level or abstracted macro-model for top- level analysis. Vectored or vectorless simulations can align functional states to mimic worst case stress scenarios.
Ansys Totem/Totem-SC provide a comprehensive EM signoff which includes power/signal EM analysis, modeling joule-heating, wire coupling and self-heating of the FinFETs and their impact on the interconnects. The flow has been enabled by all major foundries and used by all customers doing FinFET designs. Statistical EM Budgeting is also enabled in Totem to address demands for automotive and other mission critical applications.
IP integration is one of the biggest challenges faced by SoC designers. The same IP operating in two different modes can experience very different voltage drop. Totem and Totem-SC accurately model and characterize IP for different modes of operation in top-level voltage drop analysis. The IP model includes electrical and physical properties, along with any embedded constraints for power integrity signoff at the SoC level by RedHawk-SC.
Ansys Totem/Totem-SC’s GUI offers advanced query and debugging capabilities including customizable maps and debug views to help identify and fix design weakness. They also enable what-if analysis to make quick design fixes before finalizing changes in the design. This significantly speeds up the turnaround compared to traditional flows where fixes first need to pass through expensive LVS and RC extraction before doing EM/IR analysis.
Ansys Totem-SC is built on the SeaScape big data analytics platform that is designed for cloud execution on 1,000s of CPU cores with near linear scalability. This gives Totem-SC extremely high capacity and fast execution with low memory per core and instant start.
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