Join us for the Ansys IDEAS India User Conference 2024 — a place to catch up on industry best practices and the latest Semiconductor design advances. IDEAS will explore future trends with keynotes from industry leaders and offer technical insights from expert chip designers from many of the world’s top semiconductor companies.
Date/Time:
November 20, 2024
9:00 am - 4:30 pm (IST)
Location:
Bengaluru, India
Venue details will be shared with invitees.
Limited Seats | Invitation-only Event
Max capacity has been reached!
At this premier conference, you will:
IDEAS India is your opportunity to deepen your understanding of power-noise-reliability sign-off for Chip-Package systems, enhance your skills, and advance your engineering capabilities. Don’t miss this chance to be part of the conversation shaping the future of technology.
Time | Session | Speakers | ||
9:00 am - 10:00 am | Registration + Hi-Tea | |||
10:00 am - 10:15 am | Welcome & Inauguration | Jai Pollayil | ||
10:15 am - 10:45 am | Industry Keynote | Balajee Sowrirajan | ||
10:45 am - 11:15 am | Ansys Keynote | John Lee | ||
11:15 am - 11:30 am | Tea/Coffee Break | |||
| Track 1: Advanced SOC Power Integrity & Reliability | Track 2: Power-Signal-Thermal-ESD Integrity across RTL / Custom IP / IC / 3DIC | ||
| Session | Speakers | Session | Speakers |
11:30 am - 12:00 pm | Conquering IR ECO complexity with PrimeClosure | Raghavendra Swami Sadhu | Backside power delivery and advanced technology EM/IR analysis in Totem | Anil Dsouza |
12:00 pm - 12:30 pm | Maximizing IR signoff coverage using Sigma-AV and its benefit on PPA | Sandeep Gajbhare | Comprehensive Electrical & Thermal integrity of Power Management IC using a new Integrated solution | Girish Bijjal |
12:30 pm - 1:00 pm | Accelerating Full Flat EMIR Sign-off of Multi-billion Instance Design using RedHawk-SC ROM (Reduced Order Model) | Raja Ramachandra Rao & Satyaki Mandal | Optimizing Standard cell library development flow using “ParagonX” – EDA tool for IC layout parasitics analysis | Ravi JN & Santhosh Kamatam |
1:00 om - 2:00 pm | Lunch Break | |||
2:00 pm - 2:30 pm | An efficient methodology for Multi-PVT EMIR analysis of Large SOCs | Ramesh Aggarwal | Signal and Power Integrity analysis of Silicon Interposer for multi-chiplet integration | Gangaraju M & Yadavalli Jagadeeswari |
2:30 pm - 3:00 pm | Accounting for IR Drop in Static Timing Analysis: A Path to Accurate Delay Estimation | Purushotham Reddy N & Manoj Varama S | Comprehensive Thermal Analysis of 3DIC design using Redhawk_SC-ElectroThermal (RHSC-ET | Rishikanth Mekala & Abhishek Chinchani |
3:00 pm - 3:30 pm | Novel method of Vectorless IR Analysis for DFT | Arun CS | Accelerated ESD Sign-off with Pathfinder-SC: An Efficient and Scalable Approach | Smaritha Kasukurthi |
3:30 pm - 4:00 pm | Optimizing Power Integrity with RHSC in Smart PDN Framework Qualcomm | Gaurav Jain & Rajender Nune | An Integrated Approach to Power Analysis & Optimization: Synergizing Emulation, RTL Design, and Physical Design | Neeraj Dwivedi |
4:00 pm - 4:30 pm | Robust techniques for IR prediction | Sayani Das | A Novel approach to cost-Efficient Hybrid Cloud Solutions with SeaScape's DataLake and Micro-Resiliency | Chandrakumar A |
4:30 pm - 4:35 pm | Concluding Remarks |
| Concluding Remarks |
|
4:35 pm - 5:00 pm | Tea & Networking | |||
