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Ansys ParagonX
IC Layout Parasitics Analysis and Debugging Software

Many thousands of layout parasitics dominate integrated circuit (IC) performance. ParagonX provides early, fast, and easy parasitic analysis with visual debugging and root-cause detection.

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Intelligent Analysis, Visualization, and Debugging Tool for IC Layout Parasitics

ParagonX lets IC design engineers shift left to quickly explore and find the root causes of parasitic-induced design issues. It enhances existing EDA workflows with powerful analytics and visual feedback for identifying the root causes of layout parasitics’ impact on performance, precision, robustness, and reliability earlier in the design cycle.

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    Resistance analysis
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    Fast, efficient debug capability
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    Capacitance/coupling analysis
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    RC delay, AC simulation, and transient simulation
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    Net and device comparison and matching verification
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    Netlist comparison
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    Netlist structural analysis
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    QA and verification: extraction, settings, PDK versions, design revisions
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Quick Specs

ParagonX is a process-agnostic tool that identifies parasitic-related design issues at an early layout stage, even before the design is LVS clean. Understanding the impact of layout parasitics is critical, especially for designs manufactured with advanced process nodes. This avoids productivity delays from performance bottlenecks and weak points later in the design process. With its unrivaled speed and capacity to handle huge netlists, IC layout engineers can find root causes and fix parasitic issues, leading to enhanced design quality and shorter design cycles.

  • Unrivalled speed and capacity
  • Easy visualization features
  • Powerful root-cause debugging
  • Python extensible
  • Automated net and device matching analysis
  • Automated ERC verification
  • Process agnostic
Image of Ansys Pharos performing on-silicon electromagnetic crosstalk analysis

“With ParagonX, I can find a weak point on a 20GB extract in minutes, taking me right to the coordinates of the problematic area.”

Ken Dyer, Principal Analog Design Engineer, Microsoft

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Industry-proven tool to analyze layout parasitics at an early design stage

ParagonX identifies parasitic-related design issues at an early layout stage, even before the layout is complete. It requires a bare minimum set of inputs and easily handles designs such as SerDes, optical transceivers, power management ICs, SRAMs, clocks, precision analog, etc. Its speed and easy-to-use interface let designers quickly find root-causes and fix any parasitic-related issues in the layout.

Diakopto Capabilities

 

Key Features

The fastest and most accurate parasitic analysis tool for non-LVS clean IC design layout. It is process agnostic and is applicable to the most advanced technology nodes and any design style. The easy-to-use interface makes ParagonX an interactive designer’s tool that works in all layout flows.

  • High speed and capacity
  • Easy-to-use GUI
  • Debug root causes
  • Sensitivity-driven design
  • What-if compatibility with EDA tools
  • Net and device matching
  • ERC verification
  • Python extensibility

Ansys ParagonX can easily handle large netlists, and provide debugging results as quickly as minutes or hours.

Ansys ParagonX is the only solution that not only finds the parasitics issues but also the root cause of the problem.

This makes parasitic debugging and layout optimization easy and efficient.

ParagonX offers easy integration with popular custom layout tools.

The analysis includes coupling capacitances, point to point resistance, RC delays, instance matching, 2 or N nets.

It can detect potential circuit errors early in the chip design process and ensures the functionality, reliability, and performance of ICs.

Ansys ParagonX is Python extensible so that you can create your own workflows to address your unique engineering challenges.

Ansys software is accessible

It's vital to Ansys that all users, including those with disabilities, can access our products. As such, we endeavor to follow accessibility requirements based on the US Access Board (Section 508), Web Content Accessibility Guidelines (WCAG), and the current format of the Voluntary Product Accessibility Template (VPAT® ).

View VPAT Reports