ASIC Design Flow: What is ASIC Design?

ASIC, short for application-specific integrated circuit, is a specialized type of integrated circuit meticulously designed to perform a specific function or set of functions within an electronic system. Unlike general-purpose microprocessors in everyday electronic devices like your microwave or TV box, ASICs are tailor-made for a particular application, offering unparalleled efficiency and performance.

ASICs encompass a diverse range of electronic products, minimizing external electronic circuitry requirements. Due to their custom-made nature, tailored for specific applications, ASIC development can incur higher costs. However, this expense can be justified and even deemed cost-effective when designing for high-volume products.

There are two primary methods of ASIC design:

• Gate array (semi-custom design)
• Full custom design

Semi-custom design is divided into a few groups. The classification of ASICs is shown below:

Sometimes, programmable ASICs are considered separate from semi-custom ASICs. Other ASIC classifications are shown below:

Full-custom design: The full-custom method is more complex and costly, but it can do much more than the gate array method. The size of the ASIC decreases significantly as the design incorporates only the necessary gates and electronics, and unused gates are deleted. These ASICs are designed for a specific purpose and support a particular function in the end product.

Semi-custom ASIC: This approach involves predefining diffused layers, transistors, and other active devices to minimize initial design efforts, which reduces non-recurring engineering costs.  The production cycles are significantly shorter because the metallization process is utilized, which is a relatively swift process compared to full custom design. During the final design phase, engineers manipulate specific switches, opening and closing them to guide the chip's behavior according to the desired specifications.

Standard cell-based ASIC: This type of ASIC uses predesigned logic cells called standard cells, such as gates, multiplexers, and flip-flops. Standard cells are made using full-custom design methodology and serve as basic building blocks for ASIC design, ensuring the same performance and flexibility but reducing time and risk.

Gate-array based ASIC: In this category of ASIC, transistors, logic gates, and other active devices are created and manufactured on a silicon wafer, while interconnects are not formed during fabrication. The pre-established arrangement of transistors on the gate array is referred to as the base array, and the smallest repetitive element forming the gate array is called the base cell. Several advantages accompany this approach, including a shorter turnaround time, higher logic density, and customization of contact layers.

Programmable ASIC: This type of ASIC can be programmed at the hardware level after manufacturing. Unlike traditional ASICs, which are custom-designed and fabricated for specific applications, programmable ASICs offer a degree of flexibility and reprogramming. Programmable logic devices (PLDs) and field-programmable gate arrays (FPGAs) are perfect examples of programmable ASICs. 

ASICs find applications in various industries, each leveraging the technology for unique purposes. Here are some prominent sectors in which ASICs play a pivotal role:

Consumer electronics: ASICs are omnipresent in consumer electronics, powering devices such as smartphones, digital cameras, and smart TVs. Their ability to provide tailored solutions enhances these gadgets’ overall performance and power efficiency.

Telecommunications: ASICs are employed in networking equipment, routers, and communication devices. Their custom-designed nature ensures optimal functionality and speed in processing data.

Automotive industry: ASICs contribute significantly to the automotive industry, in which they are integrated into various systems like engine control units (ECUs), advanced driver-assistance systems (ADAS), and infotainment systems.

Healthcare: Medical devices, diagnostic equipment, and imaging systems often incorporate ASICs to meet the stringent requirements of precision, reliability, and power efficiency.

Designing an ASIC is a meticulous process involving several stages, each contributing to creating a highly specialized chip. The key phases of ASIC design include:

Specification and requirements: This is the first stage of ASIC design flow, which involves defining the specifications and requirements to start the design process. It consists gathering input from pertinent stakeholders and translating the overarching product specifications into detailed technical specifications. Expected outputs, performance objectives, power consumption targets, and other essential parameters must be clearly outlined.

Architecture design: Once the specifications are in place, the architecture of the ASIC is designed. This involves determining the overall structure, the arrangement of functional blocks, and the interconnections between these blocks. Engineers must brainstorm many possible ideas and select the ideal approach by carefully considering performance implications, technical feasibility, and hardware resources while keeping the overall cost within the assigned budget.

RTL design: Register-transfer level (RTL) design involves describing the functionality of the ASIC using a hardware description language (HDL). This phase serves as a bridge between the abstract architectural design and the physical implementation.

Verification: Verification ensures that the ASIC meets the specified requirements by testing and simulating the design on the test bench. This stage is critical in identifying and rectifying any design flaws or issues.

Synthesis and implementation:  During synthesis, RTL code is converted into a gate-level netlist, representing the ASIC's physical implementation. This netlist is translated into a layout, and the physical design is optimized for power consumption, speed, and area.

Signoff and tape-out: After completing the physical layout, the next step is to verify the physical design against the design rules recommended by the foundry. Engineers perform layout-versus-schematic (LVS) checks and design rule checking, which uses simulation tools to modify the design where required. This process is called signoff. Once the design passes the specified design rules, it is taped out and sent to the foundry for manufacturing.

Manufacturing: The final step involves manufacturing the ASIC using semiconductor fabrication processes. This step requires collaboration with semiconductor foundries capable of producing the custom-designed chip. Selecting the right foundry helps achieve the desired outcome.

Performance optimization: ASICs are designed to excel in specific tasks, featuring only essential circuitry for their dedicated functions. Their streamlined design contributes unparalleled performance and efficiency, surpassing general-purpose processors in terms of reduced size and lower power consumption.

Power efficiency: The custom nature of ASICs allows for the eliminating of unnecessary components, leading to improved power efficiency and reduced energy consumption.

Space optimization: ASICs can be tailored to fit specific form factors, enabling space-efficient designs in electronic devices.

Cost effective in volume: While the initial costs of ASIC design and manufacturing can be substantial, they become cost effective when produced in large volumes due to the absence of redundant components.

Enhancing performance and efficiency has consistently topped the priority list in the electronics industry. The industry-wide impact of ASICs’ application-specific nature is evident, propelling innovation and elevating electronic devices’ capabilities. Making the design process of ASICs more efficient, rapid, and cost-effective requires judicious selection of design and simulation software. With escalating speeds and diminishing sizes, designers must move beyond conventional techniques and address emerging multiphysics challenges.

Learn more about the importance of multiphysics simulation here: Ansys Semiconductor Solutions

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