Empower Innovation at IDEAS 2023 Digital Forum
ANSYS’ VIRTUAL USER CONFERENCE FOR ELECTRONICS, SEMICONDUCTORS AND PHOTONICS DESIGNERS
Join us for the IDEAS Digital Forum — a place to catch up on industry best practices and the latest semiconductor, electronic, and photonic design advances. IDEAS will explore future trends with keynotes from industry leaders and offer technical insights by expert chip designers from many of the world’s largest electronic and semiconductor companies.
Are you ready to empower innovation at this year’s IDEAS?
NOV 30, 2023 | 8 AM PST
FEATURED SPEAKERS
Agenda
Nov 30, 2023
Opening Keynote: Leveraging AI/ML for Engineering Simulation
8:00 AM - 8:15 AM PDT
Prith Banerjee
Chief Technology Officer, Ansys
Dr. Prith Banerjee is the Chief Technology Officer of Ansys. He is responsible for leading the evolution of Ansys’ Technology strategy and will champion the company’s next phase of innovation and growth. Previously, he was Senior Client Partner at Korn Ferry where he was responsible for IOT and Digital Transformation in the Global Industrial Practice. Prior to that, he was Executive Vice President, Chief Technology Officer of Schneider Electric. Previously, he was Managing Director of Global Technology Research and Development at Accenture. Formerly, he was Chief Technology Officer and Executive Vice President of ABB, a power and automation company in Zurich, Switzerland. Earlier, he was Senior Vice President of Research at HP and Director of HP Labs. Formerly, he was Dean of the College of Engineering at the University of Illinois at Chicago. Formerly, he was the Walter P. Murphy Professor and Chairman of Electrical and Computer Engineering at Northwestern University. Prior to that, he was Professor of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. In 2000, he founded AccelChip, a developer of products for electronic design automation, which was acquired by Xilinx Inc. in 2006. During 2005-2011, he was Founder, Chairman and Chief Scientist of BINACHIP Inc., a developer of products in electronic design automation. His research interests are in electronic design automation, and parallel computing, and he is the author of about 350 research papers in journals and conferences. He was listed in the FastCompany list of 100 top business leaders in 2009. He is a Fellow of the AAAS, ACM and IEEE, and a recipient of the 1996 ASEE Terman Award and the 1987 NSF Presidential Young Investigator Award. He received a B.Tech. (President's Gold Medalist) in electronics engineering from the Indian Institute of Technology, Kharagpur, and an M.S. and Ph.D. in electrical engineering from the University of Illinois, Urbana
Keynote: Chiplets – How does EDA Eco System Need To Evolve?
8:15 AM - 8:30 AM PDT
Lalitha Immaneni
Vice President, Intel
Lalitha Immaneni is a Vice President of Engineering in the Assembly Test Technology Development organization for Intel Corporation. Lalitha manages the “Architecture, Design & Technology Solutions” team, which spans multiple geographies such as the United States, Malaysia, and India. She is responsible for substrate/silicon assembly and board design rule development. She designs building blocks for emerging package technologies and electrical and physical design methodologies for packaging, executes product package design, provides product electrical analysis support, and drives product architectures for Intel. Lalitha owns centralized package and board flows/tools for Intel’s packaging and board design needs and enables EDA ecosystem readiness. She also leads architecture and design enabling services for Intel Foundry. Recently, she led the delivery of Intel Foundry Services’ Package Assembly Design Kit. She is currently focused on EDA ecosystem enablement, interoperable formats, and standards for chiplets. Presently, Lalitha is the Assembly Test Technology Development Staff-level Diversity & Inclusion team sponsor and a formal mentor, coach, and sponsor to many technical females and diverse employees. She holds both bachelor’s and master’s degrees in computer science from Arizona State University, with an emphasis on computer graphics and software engineering.
Technology Innovation Panel – How Leading Customers are Radically Rethinking Power Integrity Analysis and Breaking Through the Status Quo
8:31 AM - 9:09 AM PDT
Ed Sperling
Editor-in-Chief, SemiEngineering
Ed Sperling is the editor in chief of Semiconductor Engineering. He is a technology industry veteran and frequent moderator and speaker in Silicon Valley. Sperling is a former contributing editor at Forbes, where he wrote nearly 200 articles about business and technology issues affecting IT and CIOs. He was previously editor in chief of Electronic News and Electronic Business, and before that he held top editorial positions at Ziff-Davis and CMP Publications. Prior to that he was a daily newspaper investigative reporter covering crime and corruption.
Technology Keynote: 3D Thermal Challenges and the Way Forward
9:10 AM - 9:30 AM PDT
Murat Becer
Vice President, Ansys
SigmaDVD: Enabling breakthrough methodologies for IR prevention, analysis coverage, and accelerated design closure
9:30 AM - 10:00 AM PDT
Technology scaling tends to increase power density and metal impedance, making it increasingly difficult to confidently sign off power integrity while meeting PPA and schedule requirements. Ensuring high confidence power integrity in large state of the art designs requires new approaches to traditional static and dynamic IR drop analyses. This presentation introduces a methodology that leverages the revolutionary SigmaDVD technology to enable IR prevention (shift left), power noise analysis with excellent coverage, and efficient design closure with optimized PPA.
Chip Stratakos
Partner, Physical Design, Microsoft
Chip leads the Physical Design team for the AI custom silicon products at Microsoft. He started his career at Intel and also worked at Broadcom and Google. He holds a BSEE from Stanford.
Novel CAD Methodology for IR Drop and Reliability Verification of Stacked Dies (3D-IC)
9:30 AM - 10:00 AM PDT
As Stacked Die usage continues to grow, a robust CAD solution around vendor EMIR tools is needed for quick and efficient sign-off. A Flow around the vendor tool needs to account for # number of dies and succinctly pinpoint and summarize problem areas in a 3D stack that cannot be found in single-die runs.
Matthew Jastrzebski
Engineer, Intel Corporation
3D-IC RV CAD Engineer at Intel, focused on delivering 3D EMIR solutions to client and servers teams
High-Performance Design with Rapid RTL Profiling of Critical Power Scenarios
9:30 AM - 10:00 AM PDT
High current events (di/dt) in the SoC are the result of the sudden high current demand caused by a large number of simultaneous switching activities from the workload. Unless appropriate mitigation strategies are in place, these di/dt events can cause significant voltage drops in the power grid. From an analysis of RTL level switching activity profiles of representative workloads and their dynamic power profiles, the critical windows where adverse di/dt events might occur can be revealed. Consequently, RTL stage solutions for better Power & Performance can be implemented in a timely manner, during the design phase.
Alexander Pivovarov
SMTS, AMD
With over 10 years of experience in the semi-conductor industry, Alexander has had significant exposure to design verification and power convergence, both at IP level and at SoC. He has worked on analyzing and driving power optimization across numerous projects and has developed novel methodologies for getting more accurate results.
Laying the Foundations for Optical Pass-Through Links’ Design
9:30 AM - 10:00 AM PDT
Optical pass-through (OPT) links have been proposed in scalable, always on, all-to-all (A2A) connected switchless optical networks as a promising solution to reduce the amount of connections against A2A network fabrics based on a brute force approach. Thus, it is of crucial importance to understand the design challenges, if any, of optical links for intra-node communications. In this work, we propose, for the first time, a design-space exploration that leverages the bit error rate (BER) performance to evaluate the viability of OPT links in serviceable high-performance computing systems. In particular, we use Ansys Lumerical INTERCONNECT to analyze the BER performance for optical links at 16 Gbps.
Luca Ramini
Research Scientist, Hewlett Packard Labs
Dr. Luca Ramini is a research scientist in the Large Scale Integrated Photonics Lab at Hewlett Packard Enterprise. Luca’s research interests include the design of photonics circuits and optical networks. Luca was Postdoc at the University of Ferrara, contract Professor at the University of Verona, and photonics designer at STMicroelectronics.
A Novel approach to cost-Efficient Hybrid Cloud Solutions with SeaScape's DataLake and Micro-Resiliency
9:30 AM - 10:00 AM PDT
Mohit Srivastava
Staff Engineer
Mohit has 7+ years of experience in the field of Design Automation, Standard cell and IO development. At Arm, as a Staff Software Engineer, I am responsible for the methodology implementation, looking after the EDA issues which are raised at Arm.
ML-Based Multiphysics OptimizationsFrom Concept to Applications
9:30 AM - 10:10 AM PDT
Jerome Toublanc
Business Development executive
A Multiphysics Simulation Flow for High Performance MMIC Products for 5G and RF Applications
9:30 AM - 10:00 AM PDT
Pressure on cost and performance of MMIC products for 5G and RF applications requires EM-based optimization of designs to gain competitive advantage. Moreover, the need to reduce size requires packing many components in a limited space, leading to increased temperatures. To make sure that such temperatures and the related mechanical stress levels remain under reliability limits, Multiphysics simulations are needed at system level, including chip, package, board and cooling blocks. To tackle this challenge, Ampleon engineers use Ansys tools. In more detail, Raptor X is used to simulate full MMIC designs on low-resistivity substrates, which are especially challenging to model due to the slow-wave propagation. Ansoft 3D layout is used to import the layout into Electronic Desktop (AEDT) where it is combined with board, package, and cooling blocks for system level Multiphysics simulations in AEDT/Mechanical. At this stage, engineers are not only able to optimize system designs to make sure that temperature and stress levels remain under safe limits, but also to explore different cooling options. Having EM and Multiphysics tools under the same roof with a simple interface improves efficiency, boost productivity, and enables cutting-edge designs of high-performance products and allows Ampleon to save costs gaining market competitiveness.
Vittorio Cuoco
Senior Principal Modeling Engineer - Multiphysics Simulations Competence Manager, Ampelon
A Novel Methodology for EM/IR analysis of Complex LDO/Power Gated Designs
9:30 AM - 10:00 AM PDT
RF/Automobiles chips are more complex in designs and operate at ultra-high frequencies. Qualcomm custom devices make the design complex compared to other analog and digital designs. Hence there is a requirement for a flow which is dynamic, schematic/layout driven, and which supports the complexity in the chip designs and meet Qualcomm chipset criteria of EM sign off. When head switches and regulators are present, It is even more difficult to make the setup for the end users. In conventional flow, the internal net was brought to the top level and analyzed. The critical part is that we have an internal P/G domain which cannot be always defined as global due to same names at the next hierarchies sometimes. The tool needs to be more intelligent to handle multiple domains at different levels. The paper presents a novel methodology with a customizable GUI flow to extract the internal P/G domains and to handle the P/G domains after head switches and regulators which are not directly connected to voltage sources.
Pavan Bilekallu
Lead Engineer, Layout, Qualcomm India Pvt. Ltd.
I am a Lead Engineer, Layout at Qualcomm. I work with the team to enable the Totem EM/IR analysis tool for reliability tests of the modules.
Accuracy and Performance benchmarks for Gate-level Power Integrity Signoff with RedHawk-SC Advanced Power Analytics
9:30 AM - 10:00 AM PDT
It has been a known challenge to signoff PDN for gate-level netlist with gate vectors as the vectors are not available until late in design cycle. For PDN signoff, currently the designers either wait for gate vectors to be available or simulate RTL vectors using simulation tools. However, using RTL vectors with gate netlist brings their own challenges with regards to name-mapping differences between the two; low coverage of RTL FSDBs on combinational logic; need of accurate delay-aware event propagation and runtime performance issues for multi-mode long RTL vector sets. In this paper we present the results of accuracy and performance benchmarks for Long Vector Simulations in Automotive SoC usecases using Dynamic Power View (RedHawk-SC Advanced Power Analytics Platform). The tool uses distributed SeaScape architecture to provide detailed analysis of multi-corner, multi-domain, cell/clock/hierarchy wise debug reports, smart auto-name mapping algorithm with flexibility to add user mapping files to drive 90%+ mapping coverages and fast & accurate event propagation for long (ms+) RTL Vectors on SoC designs with multi-million gate count. The results from gate power on a reference automotive SoC design are within 10% of Silicon, with couple of hrs of scalable performance runtimes. The Dynamic Power View is also leveraged for accurate cycle-by-cycle power over time analysis to drive multi-mode power analysis for EMIR Power Integrity Signoff.
Love Gupta
Principal Design Engineer, NXP
Love Gupta holds a Bachelor’s degree in Electronics Instrumentation and Control engineering from Thapar University, Patiala. He has around 11 years experience in VLSI industry. During this time he is mainly working with PDN tools for EMIR closure of complex Automotive SoCs. He is also involved in developing PDN design flow methodologies for new technology nodes.
Optimizing Power MOSFET Design with optiSLang AI/ML and Ansys Totem PMIC Utility
10:00 AM - 10:30 AM PDT
Mandar Deshpande
Technical Staff Engineer, CAD, Microchip Technology Inc.
Silicon Interposer Extraction Using Ansys RaptorX
10:00 AM - 10:30 AM PDT
Garth Sundberg
Senior Principal Engineer, Ansys
Dr. Garth Sundberg is a Senior Principal Engineer at Ansys where he works with on-die electromagnetic extraction including signal and power integrity, RF-IC, interposers, quantum computing, and die/package co-simulations. He also works on system level signal and power integrity, electrical and thermal modeling of PCBs, connectors, and EMI/EMC.
SigmaDVD: High Coverage Solution for Power Integrity Signoff
10:00 AM - 10:30 AM PDT
SigmaDVD (sDVD) is a unique simulation method that provides complete power grid noise coverage for 100% of the design instances. This novel simulation technique generates tens of thousands of unique switching scenarios for each instance independently, using Monte Carlo techniques, and gathers the results into a distribution with a known three-sigma DVD value (sDVD) per instance. This analysis closes a known gap in power grid noise coverage available from other methods, such as vectorbased and vectorless direct transient simulations as well as BQM. The main considerations when comparing this new IR-Drop flow with other techniques are coverage (what % of hotspots from other IR-Drop methods does sDVD cover?) and how to handle the increase in hotspots/violating instances caused by the massive increase in noise coverage. We quantified this new flow's coverage capabilities through heatmap comparisons. In this presentation, we will first discuss the theory of sDVD, various trials we conducted to compare sDVD with other IR-Drop methods, and main conclusions (such as cost/coverage) based on our analyses. To demonstrate the added value from sDVD, we investigated sDVD's coverage of post-silicon identified outliers.
Anusha Vemuri
Physical Design Methodology Engineer, NVIDIA
Anusha Vemuri works at NVIDIA as a Physical Design Methodology Engineer in the Hardware-VLSI team. She studied at UCLA for her Bachelors and Masters in Electrical Engineering and graduated in December, 2020.
Optimizing Ansys Redhawk-SC with AMD Over InfiniBand Interconnect
10:00 AM - 10:30 AM PDT
Azure provides a flexible and scalable EDA environment, with a variety of HPC services and resources to meet the demanding requirements of electronic design workflows. InfiniBand interconnect is one such service. This presentation showcases a collaborative innovation involving Azure, Ansys, and AMD, focusing on harnessing Azure's InfiniBand-based storage solution to overcome the limitations of traditional NFS-based compute grid. By doing so, it unlocks the full potential of the cloud in terms of flexibility and scalability for EDA By combining the power of Azure's cloud infrastructure with Ansys' Redhawk-SC, AMD chip designers can accelerate their design iterations and achieve optimized results for complex electronic systems.
Andy Chan
Lead, Microsoft Semiconductor Community, Microsoft
Andy Chan is an award-winning, innovative, and customer-focused leader for Microsoft Azure's semiconductor community, with over 20 years of experience in Semiconductor and HPC-related roles. Andy is also a member of Microsoft's Platinum Club, which recognizes and rewards individuals who consistently perform at the highest level and directly contribute to the company's success. He is based in Portland, Oregon.
A Comprehensive Thermal Solution in Advanced Large Scale 3DIC Design
10:00 AM - 10:30 AM PDT
The pursuit of high integration and high performance 3DIC design makes the number of cells per unit area of the chip increase and thermal coupling between cell is intensified. Meanwhile, with narrow 3-D fin structure and lower thermal conductivity in substrate, local FinFET device temperature is higher compared to planar MOS structure. In addition, the joule heat between wires in limited space becomes severe. Narrower physical wires, higher current density, increasing impact of wire temperature on EM limit, all these factors can lead to rise of the chip temperature and worsen the electromigration(EM) phenomenon, such as open or short. To avoid function failure caused by reliability-related problems, designer restricts the design excessively with whole die set to a value higher than the maximum operating temperature in traditional flow, which causes difficulty to iterate and even failure to sign-off. So the accurate "Thermal aware EM sign-off" is a must for advanced 3DIC design. Different from the traditional flow, our flow can model the realistic heat dissipation environment of the complicated 3DIC accurately, and meanwhile take the thermal coupling of the instance, and the wire-to-wire joule heat into account to analyze the thermal convergence process precisely. For different layers and locations, different temperatures (Tj) are generated. The realistic spatial tempatrue distribution scenario generated by system-level thermal analysis can replace the coarse global temperature setting in traditional EM analysis flow. With the thermal-aware EM flow, we can avoid over-design and under-design. And the simulation results can be used to provide guidance for the heat dissipation design of the system. keywords : thermal-aware, EM-analysis, boudary condiction, system-level
Ping Ding
Backend Designeer, Sanechips
Ding Ping, joined Sanechips in 2019 and worked in Backend Design Dept.. Mainly engaged in chip power integrity signoff and power consumption analysis and other related work. Have extensive experience in power signoff for advanced process nodes.
Graphics workload-based power trends and optimizations using PowerArtist
10:00 AM - 10:30 AM PDT
This presentation is about analyzing real-world workloads on GFX RTL designs, emphasizing the discovery of optimization opportunities not easily discerned through synthetic vectors or unit-level testing. The challenge lies in efficiently processing stimuli involving tens of millions of cycles on designs of multiple million instances all within a reasonable timeframe of less than 48-hours. In PowerArtist, this can be achieved by enabling the distributed GAF (using FSDB) based reduction flow. We also utilize the average power data computed using SAIF to track relative power trends through automated regressions at the GFX IP level. This approach resulted in the discovery of significant power optimization opportunity at the GFX IP level. Furthermore, it helped us successfully identify regressions in power between two successive versions of the GFX IP using relative RTL trend tracking technique. Overall, this helps with left shifting the GFX IP level power analysis and optimization effort and avoid late RTL surprises. This directly translates into better perf-per-watt for the product.
Sandesh Saokar
Graphics Hardware Engineer, Intel
Leveraging Scan Vectorless for ATPG Robustness
10:00 AM - 10:30 AM PDT
Typically, IR drop analysis targeted only for the functional mode use cases. ATPG modes, especially stuck-at-fault analysis in Design for Testability (DFT) is not considered for DvD as the frequency of operation is lower. However, in scan mode, simultaneous switching of large number of registers give rise to high peak current and di/dt effects which, when coupled with package inductance is bound to introduce significant IR drop issues. It also captures secondary effects such as unintentional switching in the data path and combinational logic downstream of the flops. VCD based analysis is the most common method to annotate the activity on the scan flops. However, securing the VCDs for multiple cores and the duration of VCDs to cover switching activity of all scan chains is a huge challenge. This paper talks about the work done to perform vector less scan mode analysis, using an early-stage design data without the need of gate VCD which is available very late in the design stage. This RedHawk-SC based scan vector less flow demonstrates a unified setup which provides seamless method to consume scan chain configuration along with the pattern annotation without involving heavy vector generation process. The irdrop results from this method correlates very well with the actual VCD based dynamic irdrop analysis.
Mohit Jain
Principal Engineer, Qualcomm
Revolutionizing Chip Design: Python-Powered Workflow with Gdsfactory and Lumerical-Ansys Integration"
10:00 AM - 10:30 AM PDT
For the efficient development, verification, and validation of integrated circuits and components, it's crucial to establish a streamlined, customizable, and extensible workflow. Python has emerged as the go-to programming language for a wide range of applications, including machine learning, scientific computing, and engineering. Enter Gdsfactory, a Python library designed to facilitate the creation of chips across various domains such as Photonics, Analog, Quantum, MEMs, and more. Gdsfactory offers a unified syntax that simplifies the entire process of designing, verifying, and validating these complex systems. In this presentation, we'll showcase the seamless schematic-driven workflow of Lumerical-Ansys interconnect in combination with the Gdsfactory design automation tool. This combination delivers an end-to-end workflow that seamlessly integrates layout, verification, and validation. It leverages an extensible, open-source, Python-powered approach to transform your chip designs into fully validated products, ensuring a smooth and efficient development cycle.
Joaquin Matres
Photonics Engineer, Google X
Joaquin Matres received his Engineering (2009), M.Sc. (2010) and PhD (2014) degree in Telecommunications from the Universidad Politecnica de Valencia, Spain. For his PhD he built CMOS-compatible all-optical switches and logic gates at IMEC and CEA-LETI foundries. During his 6 month internship in Intel Corporation and 2.5 years in Hewlett Packard Labs, he worked on hybrid tunable lasers, wavelength selective switches and microring based optical transceivers. Then as the first engineer that joined PsiQuantum he worked on design, layout and validation of large scale Quantum computing circuits, where he was involved in most tapeouts during 3 years. Since 2020 Joaquin has been working at X Moonshot Factory (Formerly known as Google X) developing Free Space Optical Transceivers to bring affordable internet to developing countries. Joaquin is also an active developer of many open source projects such as gdsfactory
Early IR Drop Prediction Using Machine Learning for Power Grid
10:10 AM - 10:30 AM PDT
Meeting voltage drop specification has been an increasing challenge with process node shrinking, increase in layer stack and increase in power consumption. In custom design, power grid generation are not IR driven today. Grid gets implemented in layout first and then verified by tools on its robustness. This involves multiple iterations sometimes in advanced stage of design milestones which creates challenges in implementing layout edits as well as disturbs converged parameters and impact schedules. We propose a machine learning (ML) solution which works at the power grid definition phase of a custom IP, it tries to predict block level IRdrop on a given specification when no layout and placement information is available. It uses physical and electrical specifications as features to train the ML model. User can tune metal layer, width & pitch values to derive optimal power grid to proceed for physical implementation. The training data sets are design testcases run with IR analysis tools. Appropriate features like block dimension, metal layers, width, pitch of power grid are extracted along with IRdrop results for the testcases.
Anil D'Souza
CAD Engineer, Intel Technology Pvt Ltd
Optimizing Power MOSFET Design with optiSLang AI/ML and Ansys Totem PMIC Utility
10:30 AM - 11:00 AM PDT
Mandar Deshpande
Technical Staff Engineer, CAD, Microchip Technology Inc.
Revolutionizing Chip Design: Python-Powered Workflow with Gdsfactory and Lumerical-Ansys Integration"
10:30 AM - 11:00 AM PDT
For the efficient development, verification, and validation of integrated circuits and components, it's crucial to establish a streamlined, customizable, and extensible workflow. Python has emerged as the go-to programming language for a wide range of applications, including machine learning, scientific computing, and engineering. Enter Gdsfactory, a Python library designed to facilitate the creation of chips across various domains such as Photonics, Analog, Quantum, MEMs, and more. Gdsfactory offers a unified syntax that simplifies the entire process of designing, verifying, and validating these complex systems. In this presentation, we'll showcase the seamless schematic-driven workflow of Lumerical-Ansys interconnect in combination with the Gdsfactory design automation tool. This combination delivers an end-to-end workflow that seamlessly integrates layout, verification, and validation. It leverages an extensible, open-source, Python-powered approach to transform your chip designs into fully validated products, ensuring a smooth and efficient development cycle.
Joaquin Matres
Photonics Engineer, Google X
Joaquin Matres received his Engineering (2009), M.Sc. (2010) and PhD (2014) degree in Telecommunications from the Universidad Politecnica de Valencia, Spain. For his PhD he built CMOS-compatible all-optical switches and logic gates at IMEC and CEA-LETI foundries. During his 6 month internship in Intel Corporation and 2.5 years in Hewlett Packard Labs, he worked on hybrid tunable lasers, wavelength selective switches and microring based optical transceivers. Then as the first engineer that joined PsiQuantum he worked on design, layout and validation of large scale Quantum computing circuits, where he was involved in most tapeouts during 3 years. Since 2020 Joaquin has been working at X Moonshot Factory (Formerly known as Google X) developing Free Space Optical Transceivers to bring affordable internet to developing countries. Joaquin is also an active developer of many open source projects such as gdsfactory
Simulation Driven Enhancements to Photonic Integrated Circuit Devices in Tower’s PH18 Platform
10:30 AM - 11:00 AM PDT
Silicon photonics process technology is spearheading today's rapid advancements in optical fiber communication, automotive LiDAR, quantum computing, and biosensing applications. A pivotal factor in driving these innovations is the quality of the foundry's Process Design Kit (PDK), which plays a critical role in efficiently supporting user designs, thus optimizing performance, and minimizing time to market and costs. Ansys and Tower have partnered for over five years to deliver a PIC design enablement platform for Tower’s PH18 silicon photonics foundry process. During this presentation, we showcase enhancements to existing components and the development of novel components utilizing the capabilities of Ansys design tools. Our simulations yield highly favorable agreement with measurement results. Attendees can adopt the same methodology to develop the customized devices, while reducing cost of design for some of the world’s most exciting and growing markets.
Bowen Wang
Sr Staff, Tower Semiconductor
Dr. Bowen Wang became a Senior Staff Process Development SiPho Integration Engineer at Tower Semiconductor at 2022, where he dedicated his expertise to advancing the company's photonic platform development. Piror to this, he served as a Senior Engineer at Synopsys, focusing on enabling photonic Electronic Design Automation (EDA). Dr. Wang boasts over 15 years of experience in the field of photonic integrated circuits, and he earned his PhD in applied physics from Eindhoven University of Technology in the Netherlands.
Synopsys/Ansys/Keysight RF Reference Design Flow on TSMC Advanced N4P Process
10:30 AM - 11:00 AM PDT
Smartphone, automotive and IoT applications all demand 5G/6G wireless and WiFi 7 communication, networking and online activities. This is driving the development of RF designs on leading-edge, high volume process technologies. Synopsys, Ansys and Keysight will present how they teamed up with TSMC to develop an RF design reference flow using TSMC advanced N4P process that streamlines the use of advanced CMOS technology for sub-10GHz RF circuit designs. In this talk, we will describe how the TSMC N4P RF reference design flow cuts design turnaround time with modern, open, and high-quality RFIC design tools from Synopsys, Ansys and Keysight. We will address the design of typical RFIC components including a 2.4 GHz LC-VCO, a 5.8 GHz LNA, and a 10 GHz LC-VCO using Synopsys Custom Compiler™ design/layout and Synopsys PrimeSim™ Continuum circuit simulation products. These are tightly integrated with Synopsys StarRC™ parasitic extraction signoff product and Synopsys IC Validator™ physical verification product, and with accurate electromagnetic (EM) analysis provided by Ansys Helic tools and Keysight PathWave RFIC Design (GoldenGate) and RFPro products.
Keith Lanier
Technical Product Mgmt Director, Synopsys
Keith Lanier received his BS Electrical Engineering degree from North Carolina State University in 1986 and MS Electrical Engineering degree from National Technological University in 1993. From 1986-1994, he worked at Analog Devices in Greensboro, NC designing high accuracy, high speed ADCs and discrete amplifiers. From 1994-2000, he worked as a Physical Verification product applications engineer and manager at ISS and Avant! in RTP, NC. At Synopsys since 2002, he was one of the earliest custom design product champions with many different roles including Product direction, R&D, Quality, and Release Management and is currently a member of the Product Management team within the Synopsys EDA Group focused on Custom, Analog and Mixed Signal, and RF Design products.
Silicon Interposer Extraction Using Ansys RaptorX
10:30 AM - 11:00 AM PDT
Silicon interposers are an important technology to increase the functionality of electronics while reducing the power consumed and size required. Electromagnetic modeling of silicon interposers is required to achieve this reduction. The Ansys RaptorX solver is perfect for modeling silicon interposers. This presentation will demonstrate the capabilities RaptorX has which make it well suited for extracting silicon interposers. Those capabilities are capacity, speed, accuracy, the ability to model through silicon vias (TSVs), and the ability to model deep trench capacitors (DTCs). These capabilities are demonstrated by extracting an interposer with signal nets, ground nets, power nets, TSVs, and DTCs. The extraction results are shown and discussed.
Garth Sundberg
Senior Principal Engineer, Ansys
Dr. Garth Sundberg is a Senior Principal Engineer at Ansys where he works with on-die electromagnetic extraction including signal and power integrity, RF-IC, interposers, quantum computing, and die/package co-simulations. He also works on system level signal and power integrity, electrical and thermal modeling of PCBs, connectors, and EMI/EMC.
SPICE Validation of Dynamic Voltage Drops from SigmaDVD
10:30 AM - 11:00 AM PDT
Dynamic voltage drop (DVD) is an escalating problem as technology nodes shrink. Traditional DVD analysis methods lack necessary coverage to identify the location and magnitude of DVD hotspots. New tools, such as the SigmaDVD technology in Ansys RedHawk-SC, aim to improve DVD accuracy and coverage. In this work, we present results from a circuit targeted to validate SigmaDVD results. This circuit is simulated in SPICE with a fully extracted power grid, using non-Ansys tools. This validation method has been used to enhance the algorithms used by SigmaDVD, resulting in significant accuracy improvement. Analysis of one specific enhancement will be demonstrated in detail. The importance of properly accounting for correlated activity will be also discussed.
Andy Hoover
Senior Principal Technologist
Andy Hoover is the technologist for the Samsung Austin R&D Center (SARC). His 30 years experience spans device engineering, SPICE model generation, RTL design, physical design, circuit design, and design methodology. Among other things, he champions SARC’s use of SigmaDVD, collaborating with Ansys for the past 3 years.
Thermal Aware Vectorless EM/IR Sign-off for Custom-IPs
10:30 AM - 11:00 AM PDT
For High Speed Mixed signal IPs, custom digital designs are prone to EM/IR issues due to high frequency paths and custom drawn layout. At the same time, testbench setup with worst case vectors is a big challenge along with coverage concern in such simulation based run. As an alternative, vectorless mode EM/IR provides desired coverage and worst case analysis for EM purpose. Even though EM/IR is covered through heuristic based approach in industry standard tools, there's no equivalent thermal solution to include Self heat effect for transistors. This paper talks about a novel characterization based approach to mitigate Self heat risks for above mentioned designs. As a part of the solution, vendor EDA tool runs a design specific transistor characterization with Simulation models to compute thermal resistance of each transistors. Later in the flow vectorless engine calculated power is used along with the derived thermal resistance to compute device deltaT profile used by Self heat analysis.
Ayan Roy Chowdhury
Engineering Manager, Intel Technology India
Ayan Roy Chowdhury has done his graduation in Electrical Engg from Jadavpur University, India and completed masters in theoretical Computer Sc with VLSI CAD major from Indian Statistical Institute (ISI), Kolkata, India. He has 16 years of industry experience in design automation areas, focussing on backend design and signoff domains including Simulation, EM/IR, ESD, Physical verification, Extraction & Timing signoff in Intel. His special interest has been Power delivery & EM/IR where he has enabled tools & flows for different generations of internal & external technology nodes and architected signoff methodologies for IPs & SOCs in Intel. He has 15+ publications in Intel internal and different external conferences.
An Accurate System-level Transient Droop Analysis Methodology for High Performance GPGPU Power Delivery Network
10:30 AM - 11:00 AM PDT
GPGPU is commonly used in data-center, AI and high performance computing systems. To achieve higher computing performance and bandwidth, the growing current demand of GPGPU makes the power delivery network(PDN) design become more and more challenging. In this paper, we proposed an accurate system level transient voltage droop simulation methodology for high performance GPGPU PDN design and optimization. The accuracy of voltage droop mainly depends on current profiling and accurate PDN modeling. Firstly, we developed an accurate and efficient current profiling flow for system level voltage droop simulation. We used the gate level current profile to achieve result accuracy and take the advantage of RTL level current profile generated from Ansys PowerArtist tool to improve simulation efficiency. With combined usage of gate level/RTL level current, we’re able to shift PDN design to RTL design stage and to do quick iteration with accuracy. Secondly, we presented a novel PDN power model extraction methodology with board, socket and package design merged. This way enables us to consider accurate socket model impact compared with traditional separate model extraction way. Lastly, we did voltage droop lab measurement to verify the accuracy of simulation flow. The simulated voltage droop is well correlated with the measurement result.
Yuanyuan Ling
Power Integrity Engineer, Iluvatar
Yuanyuan Ling has 5 years of work experience in system level power integrity(PI) analysis. She is working at iluvatar as a power engineer, mainly focus on new PI methodology development and droop optimization for high performance GPGPU. Before that, she was at Intel for 3 years and responsible for providing package and platform power integrity solution for INTEL server CPU.
Accuracy and Performance benchmarks for Gate-level Power Integrity Signoff with RedHawk-SC Advanced Power Analytics
10:30 AM - 11:00 AM PDT
It has been a known challenge to signoff PDN for gate-level netlist with gate vectors as the vectors are not available until late in design cycle. For PDN signoff, currently the designers either wait for gate vectors to be available or simulate RTL vectors using simulation tools. However, using RTL vectors with gate netlist brings their own challenges with regards to name-mapping differences between the two; low coverage of RTL FSDBs on combinational logic; need of accurate delay-aware event propagation and runtime performance issues for multi-mode long RTL vector sets. In this paper we present the results of accuracy and performance benchmarks for Long Vector Simulations in Automotive SoC usecases using Dynamic Power View (RedHawk-SC Advanced Power Analytics Platform). The tool uses distributed SeaScape architecture to provide detailed analysis of multi-corner, multi-domain, cell/clock/hierarchy wise debug reports, smart auto-name mapping algorithm with flexibility to add user mapping files to drive 90%+ mapping coverages and fast & accurate event propagation for long (ms+) RTL Vectors on SoC designs with multi-million gate count. The results from gate power on a reference automotive SoC design are within 10% of Silicon, with couple of hrs of scalable performance runtimes. The Dynamic Power View is also leveraged for accurate cycle-by-cycle power over time analysis to drive multi-mode power analysis for EMIR Power Integrity Signoff.
Love Gupta
Principal Design Engineer, NXP
Love Gupta holds a Bachelor’s degree in Electronics Instrumentation and Control engineering from Thapar University, Patiala. He has around 11 years experience in VLSI industry. During this time he is mainly working with PDN tools for EMIR closure of complex Automotive SoCs. He is also involved in developing PDN design flow methodologies for new technology nodes.
EMA3D Charge
11:00 AM - 11:30 AM PDT
Timothy McDonald
President, EMA
Tim McDonald is President at EMA. EMA is a leading developer of technologies for engineering simulation. EMA’s engineering specialty is in applied electromagnetics. In this domain, EMA provides software and services to promote the design, certification, and performance of customers’ products. EMA is the Ansys Technology Partner behind the Ansys Electronics Plus solutions of EMC Plus and Charge Plus. Dr. McDonald holds a PhD in Applied Physics and Applied Math from Columbia University in the City of New York.
Novel Hierarchical IREM Sign-off Flow Using ROM
11:00 AM - 11:30 AM PDT
Dongyoun Yi
Staff Engineer, Samsung Electronics
Dongyoun Yi is a staff engineer at Samsung Electronics. He is currently in charge of EMIR sign-off methodology. He received the B.S. degree in computer science enginerring and the M.S. degree in electronic engineering from Seoul National University in 2010 and 2017, repectively.
Innovating Semiconductor Design with Ansys applications on AWS
11:00 AM - 11:40 AM PDT
Dnyanesh Digraskar
Principal HPC Partner Solutions Architect, AWS
The tool certification process of Ansys RedHawk-SC Electrothermal: another successful collaboration with Ansys
11:00 AM - 11:30 AM PDT
Ki Wook Jung
Staff Engineer, Foundry Business, Samsung Electronics
Dr. Ki Wook Jung graduated in 2020 with his Ph.D. in Mechanical Engineering at Stanford. He has a strong background in MEMS fabrication techniques, and embedded cooling solutions for high-power density electronics. He is currently working on developing thermal-aware design methodology for 2.5D/3D IC multi-die systems at Samsung Foundry Business.
EPDA: Bringing Layout Awareness to Photonics Simulation
11:00 AM - 11:30 AM PDT
This joint presentation with Zeqin Lu, Lead R&D Engineer at ANSYS, will review the latest progress in our EPDA collaboration. Last year, we introduced the direct link between Virtuoso and the optical device characterization tools. This year, we are adding the ability to INTERCONNECT to directly evaluate Virtuoso CurvyCore optical connectors to bring optical interconnect layout awareness to co-simulation.
Gilles LAMANT
Distinguished Engineer, Cadence Design Systems Inc
Gilles has been working with Cadence since 1989. He has lead the photonics efforts and collaboration with partners for the past 8 years.
Early Clock Tree Power Correlation at SOC: A Case Study
11:00 AM - 11:30 AM PDT
The clock tree power is one of the critical aspects to be estimated and analyzed for an SoC, as the clock network power contributes to major share in overall power of the chip. Typically, clock power estimations and analysis is performed at gate level which is late in the cycle (CTS stage), which would not provide any room for design optimization due to stringent timelines of SOC execution. So, it will be very useful to have early estimation of power on RTL, which provides more scope to optimize the design for power, much earlier in the design cycle. This paper discusses the advantages and challenges of extracting clock tree power on RTL by deploying PowerArtist tool and finding out the areas of improvement in design which helps in optimizing the design for better quality in terms of power. This paper also discusses the challenges running the PowerArtist at SOC level and provides suggestions to optimize the runtimes and report analysis.
Sri Sai Pavan Pasumarthi
Senior Engineer, Qualcomm
Integrated IR shift-left solution in construction with RedHawk-Fusion
11:00 AM - 11:30 AM PDT
Historically IR fixing has been done manually in post route stage due to lack of an integrated in-construction automation. Modern SoCs now have billions of instances , as well as the complexity of PG grid leads to billion nodes easily which requires an efficient shift-left methodology to improve the productivity. Using latest 2023_R2 RHSC with 2022.03-SP5, it was seen that overall 90% correlation between RHAF to RHSC signoff, and 100% static/ 67% dynamic IR violation reduction through the fully automated solution."
Kiran Adhikari
Hardware Engineer, Microsoft Corporation
Kiran Adhikari is a Hardware Engineer in the Azure Hardware Systems & Infrastructure group at Microsoft where he collaborates with cross-functional teams to deliver industry-leading hardware solutions improving PPA and providing faster path to design convergence. He has done extensive work in identifying bottlenecks for physical design execution and played a pivotal role in shaping physical design flows and methodologies. Prior to this, Kiran worked at Intel, focusing on physical design & SOC integration. This involved navigating complex design challenges and delivering solutions for seamless integration. Kiran received his Master of Science in Computer Engineering from Virginia Tech in 2013.
3DIC Compiler & RHSC ET
11:30 AM - 12:00 PM PDT
Kenneth Larsen
Director of Product Management and Marketing
Kenneth Larsen is a product marketing director in the Digital Design Group at Synopsys. He is a versatile leader with a strong background in defining and executing product vision, marketing strategy, inspiring product development teams, translating technology concepts into customer solutions, developing high-performance global organizations, conceiving and driving new and emerging products to scale from the ground up, guiding marketing, and enabling sales. Kenneth has a degree in electrical engineering and additional coursework in strategic growth at Columbia Business School, and Artificial Intelligence at MIT Sloan School of Management.
An Accurate System-level Transient Droop Analysis Methodology for High Performance GPGPU Power Delivery Network
11:30 AM - 12:00 PM PDT
GPGPU is commonly used in data-center, AI and high performance computing systems. To achieve higher computing performance and bandwidth, the growing current demand of GPGPU makes the power delivery network(PDN) design become more and more challenging. In this paper, we proposed an accurate system level transient voltage droop simulation methodology for high performance GPGPU PDN design and optimization. The accuracy of voltage droop mainly depends on current profiling and accurate PDN modeling. Firstly, we developed an accurate and efficient current profiling flow for system level voltage droop simulation. We used the gate level current profile to achieve result accuracy and take the advantage of RTL level current profile generated from Ansys PowerArtist tool to improve simulation efficiency. With combined usage of gate level/RTL level current, we’re able to shift PDN design to RTL design stage and to do quick iteration with accuracy. Secondly, we presented a novel PDN power model extraction methodology with board, socket and package design merged. This way enables us to consider accurate socket model impact compared with traditional separate model extraction way. Lastly, we did voltage droop lab measurement to verify the accuracy of simulation flow. The simulated voltage droop is well correlated with the measurement result.
Yuanyuan Ling
Power Integrity Engineer, Iluvatar
Yuanyuan Ling has 5 years of work experience in system level power integrity(PI) analysis. She is working at iluvatar as a power engineer, mainly focus on new PI methodology development and droop optimization for high performance GPGPU. Before that, she was at Intel for 3 years and responsible for providing package and platform power integrity solution for INTEL server CPU.
Aggressor Aware Design for Improved IR-Drop Results
11:30 AM - 12:00 PM PDT
The move to advanced technodes has many benefits, but it has created a challenge that has been previously neglectable; the aggression of neighbouring cells that are linked through the power grid – this link through the grid is known as cross-impedance. The complex grid structure that designed with pillars create cross-impedance that stretch beyond cells that share same track. Traditionally the focus of IRdrop analyses was mainly 2 aspects: i) improving self-drop –optimizing the cell’s resistive path from its power pins to the bumps. ii) handling simultaneous switching cells that share a power\ground track. To improve turn-around-time and reduce IRdrop related ECO cycles, we can tackle the problem from its origin – we can leverage Ansys Redhawk-SC platform to gather and calculate the aggression impact radius for all the cells in the library. The gathered data can be transformed to custom placement rules that will maximize cell usage while reducing overall dynamic IRdrop. At later mature design stages, we can utilize Ansys Redhawk-SC platform to combine aggressor cells in the design with their slack to a small and effective list of ECO’s that will have most overall design IRdrop improvements while having minimal impact on timing due to slack margin.
Vlad Berlin
Physical Design Engineer, Retym
A physical design engineer and leading the power integrity activity at Retym. I have worked as a Senior application engineer at Ansys, and before that I was an SI\PI engineer at Intel MIG group.
A Virtual Prototyping System for Silicon Carbide Power Modules
11:40 AM - 12:00 PM PDT
This paper describes a holistic design and simulation tool deployed for virtual prototyping of semiconductor power modules. The power module designer proceeds from concept to virtual prototype in a logical and comprehensive flow. Starting with a simple 2D DXF of the Direct Bond Copper (DBC), the module is designed through die selection and placement, layer and material property declaration, electrical connectivity, and external port definition. Automated 3D model generation is carried out through advanced Ansys scripting techniques. Multiple levels of simulation and model generation are executed through Ansys Icepak, Ansys Q3D, and SPICE. The tool has been validated on multiple onsemi Silicon-Carbide (SiC) industrial and automotive traction power modules.
James Victory
Fellow, onsemi
James Victory is currently a Fellow at onsemi, working in modeling and simulation for power discrete and module technologies. In June 2008, he co-founded Sentinel IC Technologies. Prior to that, he was the Executive Director of IC Design Enablement at Jazz Semiconductor. He started his career with Motorola in 1992 where he specialized in semiconductor device modeling for RF-analog and power technologies. He received his BSEE, MSEE, and Ph. D in electrical engineering from Arizona State University in 1990, 1992, and 1994 respectively. He has over 50 publications, including invited papers & workshop tutorials on semiconductor device modeling. He holds 6 US patents.
| TIME PDT | TITLE | SPEAKER(S) | |
|---|---|---|---|
| 8:00 AM - 8:15 AM | 8:00 AM - 8:15 AM |
Prith Banerjee
Chief Technology Officer, Ansys
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| 8:15 AM - 8:30 AM | 8:15 AM - 8:30 AM |
Lalitha Immaneni
Vice President, Intel
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| 8:31 AM - 9:09 AM | 8:31 AM - 9:09 AM |
Ed Sperling
Editor-in-Chief, SemiEngineering
Chip Stratakos
Partner, Physical Design, Microsoft
Mohit Jain
Principal Engineer, Qualcomm
Murat Becer
Vice President, Ansys
Thomas Quan
Director, TSMC
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| 9:10 AM - 9:30 AM | 9:10 AM - 9:30 AM |
Murat Becer
Vice President, Ansys
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| 9:30 AM - 10:00 AM | 9:30 AM - 10:00 AM |
Chip Stratakos
Partner, Physical Design, Microsoft
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| 9:30 AM - 10:00 AM | 9:30 AM - 10:00 AM |
Matthew Jastrzebski
Engineer, Intel Corporation
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| 9:30 AM - 10:00 AM | 9:30 AM - 10:00 AM |
Alexander Pivovarov
SMTS, AMD
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| 9:30 AM - 10:00 AM | 9:30 AM - 10:00 AM |
Luca Ramini
Research Scientist, Hewlett Packard Labs
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| 9:30 AM - 10:00 AM | 9:30 AM - 10:00 AM |
Mohit Srivastava
Staff Engineer
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| 9:30 AM - 10:10 AM | 9:30 AM - 10:10 AM |
Jerome Toublanc
Business Development executive
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| 9:30 AM - 10:00 AM | 9:30 AM - 10:00 AM |
Vittorio Cuoco
Senior Principal Modeling Engineer - Multiphysics Simulations Competence Manager, Ampelon
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| 9:30 AM - 10:00 AM | 9:30 AM - 10:00 AM |
Pavan Bilekallu
Lead Engineer, Layout, Qualcomm India Pvt. Ltd.
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| 9:30 AM - 10:00 AM | 9:30 AM - 10:00 AM |
Love Gupta
Principal Design Engineer, NXP
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| 10:00 AM - 10:30 AM | 10:00 AM - 10:30 AM |
Mandar Deshpande
Technical Staff Engineer, CAD, Microchip Technology Inc.
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| 10:00 AM - 10:30 AM | 10:00 AM - 10:30 AM |
Garth Sundberg
Senior Principal Engineer, Ansys
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| 10:00 AM - 10:30 AM | 10:00 AM - 10:30 AM |
Anusha Vemuri
Physical Design Methodology Engineer, NVIDIA
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| 10:00 AM - 10:30 AM | 10:00 AM - 10:30 AM |
Andy Chan
Lead, Microsoft Semiconductor Community, Microsoft
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| 10:00 AM - 10:30 AM | 10:00 AM - 10:30 AM |
Ping Ding
Backend Designeer, Sanechips
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| 10:00 AM - 10:30 AM | 10:00 AM - 10:30 AM |
Sandesh Saokar
Graphics Hardware Engineer, Intel
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| 10:00 AM - 10:30 AM | 10:00 AM - 10:30 AM |
Mohit Jain
Principal Engineer, Qualcomm
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| 10:00 AM - 10:30 AM | 10:00 AM - 10:30 AM |
Joaquin Matres
Photonics Engineer, Google X
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| 10:10 AM - 10:30 AM | 10:10 AM - 10:30 AM |
Anil D'Souza
CAD Engineer, Intel Technology Pvt Ltd
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| 10:30 AM - 11:00 AM | 10:30 AM - 11:00 AM |
Mandar Deshpande
Technical Staff Engineer, CAD, Microchip Technology Inc.
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| 10:30 AM - 11:00 AM | 10:30 AM - 11:00 AM |
Joaquin Matres
Photonics Engineer, Google X
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| 10:30 AM - 11:00 AM | 10:30 AM - 11:00 AM |
Bowen Wang
Sr Staff, Tower Semiconductor
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| 10:30 AM - 11:00 AM | 10:30 AM - 11:00 AM |
Keith Lanier
Technical Product Mgmt Director, Synopsys
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| 10:30 AM - 11:00 AM | 10:30 AM - 11:00 AM |
Garth Sundberg
Senior Principal Engineer, Ansys
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| 10:30 AM - 11:00 AM | 10:30 AM - 11:00 AM |
Andy Hoover
Senior Principal Technologist
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| 10:30 AM - 11:00 AM | 10:30 AM - 11:00 AM |
Ayan Roy Chowdhury
Engineering Manager, Intel Technology India
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| 10:30 AM - 11:00 AM | 10:30 AM - 11:00 AM |
Yuanyuan Ling
Power Integrity Engineer, Iluvatar
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| 10:30 AM - 11:00 AM | 10:30 AM - 11:00 AM |
Love Gupta
Principal Design Engineer, NXP
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| 11:00 AM - 11:30 AM | 11:00 AM - 11:30 AM |
Timothy McDonald
President, EMA
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| 11:00 AM - 11:30 AM | 11:00 AM - 11:30 AM |
Dongyoun Yi
Staff Engineer, Samsung Electronics
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| 11:00 AM - 11:40 AM | 11:00 AM - 11:40 AM |
Dnyanesh Digraskar
Principal HPC Partner Solutions Architect, AWS
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| 11:00 AM - 11:30 AM | 11:00 AM - 11:30 AM |
Ki Wook Jung
Staff Engineer, Foundry Business, Samsung Electronics
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| 11:00 AM - 11:30 AM | 11:00 AM - 11:30 AM |
Gilles LAMANT
Distinguished Engineer, Cadence Design Systems Inc
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| 11:00 AM - 11:30 AM | 11:00 AM - 11:30 AM |
Sri Sai Pavan Pasumarthi
Senior Engineer, Qualcomm
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| 11:00 AM - 11:30 AM | 11:00 AM - 11:30 AM |
Kiran Adhikari
Hardware Engineer, Microsoft Corporation
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| 11:30 AM - 12:00 PM | 11:30 AM - 12:00 PM |
Kenneth Larsen
Director of Product Management and Marketing
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| 11:30 AM - 12:00 PM | 11:30 AM - 12:00 PM |
Yuanyuan Ling
Power Integrity Engineer, Iluvatar
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| 11:30 AM - 12:00 PM | 11:30 AM - 12:00 PM |
Vlad Berlin
Physical Design Engineer, Retym
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| 11:40 AM - 12:00 PM | 11:40 AM - 12:00 PM |
James Victory
Fellow, onsemi
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AMPM
EXPERIENCE
IDEAS is an exciting and enriching platform for professionals in the field of chips, photonics, and electronics design. Listen to the innovative ideas and state-of-the-art experiences of your colleagues in the industry that have resulted in successful tapeouts.
