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Hands-on Workshop for IC Layout Parasitics Analysis and Debugging with ParagonX

Don't miss our upcoming workshop on Ansys ParagonX, an intelligent tool for IC layout parasitics analysis and debugging. Learn how to identify and resolve parasitic issues early, using advanced visualization and analysis. 

TIME:
November 7, 2024
12:00 PM to 4:00 PM EST

Venue:
Virtual

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Overview

Ansys ParagonX is an intelligent analysis, visualization, and debugging tool for IC layout parasitics. Its following features make it exceptional and preferred in the market.

  • With ParagonX, designers can identify and visualize the root causes of parasitic-induced design issues at an early design stage, even before the design is LVS clean
  • It is process agnostic and applies to the most advanced technology nodes and any design style
  • With its easy-to-use interface and unrivaled speed and capacity, Ansys ParagonX allows designers to identify and resolve any parasitic-related issues in the layout quickly

During this workshop, we will thoroughly explore the various features and capabilities of Ansys ParagonX. We will also demonstrate how it can be effectively used to analyze parasitic issues in your chip designs.

What attendees will learn

  • Debug and analyze the root cause of parasitic-induced design issues at an early design stage
  • Visualize these issues to gain a better understanding
  • Use ParagonX in different EDA workflows and different types of design layouts

Who should attend

  • Analog, Mixed Signal, RF, Custom Digital IC Design Engineers, Managers, Directors
  • IC Layout Engineers
  • Integration Engineers, Verification Engineers, and CAD Teams

Speakers

  • Maxim Ershov