Inductor size as well as inductor-to-inductor crosstalk can impact the die size. Ansys VeloceRF helps you design smaller devices through the use of optimization criteria and geometry constraints. In addition, it calculates coupling among any number of inductors to better optimize silicon real estate and to optimize inductors in circuit context. Ansys VeloceRF’s parametric sweep support delivers an optimal performance solution in circuit context. The foundry-verified accuracy mitigates risk in your design with silicon-proven models that help eliminate crosstalk failures.
Ansys VeloceRF currently supports over 200 unique foundry processes and works with any process down to 3nm including CMOS, BiCMOS, GaAs, SOS and SOI from all semiconductor foundries - TSMC, UMC, Global Foundries, TowerJazz and Samsung, among others. The tool integrates with leading EDA design platforms and with any LVS tool.