ANSYS ALinks for EDA - Features
Supported EDA Translations
With ALinks, your third-party IC, PCB and electronic package layout files can be imported, edited and exported in a neutral file (ANF) format. The resulting ANF file is readily available for subsequent design and analysis within ANSYS HFSS, ANSYS Q3D Extractor, ANSYS SIwave, ANSYS TPA, ANSYS Icepak and ANSYS Mechanical.
ALinks for EDA Supports
| Altium Designer | R10 |
| Cadence Allegro PCB Designer | 16.0, 16.1, 16.2, 16.3, 16.5 |
| Cadence Allegro Package Designer | 16.0, 16.1, 16.2, 16.3, 16.5 |
| Cadence SiP Layout | 16.0, 16.1, 16.2, 16.3, 16.5 |
| Cadence Virtuoso Layout | 5.10, 6.14, 6.15 (Linux only) |
| Mentor BoardStation | 8.x |
| Mentor BoardStation XE/RE | v2007, v2007.1, v2007.2, v2007.3, v2007.7 |
| Mentor Expedition PCB | v2005, v2007.1 through EE7.9 |
| Mentor Expedition via ODB++ | EE 7.9.1 and greater |
| Mentor PADS Layout | PADS PowerPCB v5.2a, v2005, v2007 |
| Zuken CR5000 | 9.x and lower, 10 and higher (Zuken translator for .anf &.cmp) |
| ODB++ |
Altium Designer R10 Mentor Expedition EE7.9.1 and greater Zuken Cadstar 12.1 (limited support) Sigrity UPD V11.1.1 (Limited support) |
User Interface
GUI
- Undo/redo
- Recent project history
- Net selection ease of use
- Show only highlighted nets
- Automated differential net identification
- Automated extended net (ENET) identification
- Automated pwr/grd identification
- Net properties
- Net properties by hovering cursor
- Net filtering
- Detect close edges
- Measure
- Check net length
- Calculate electrical properties (R, L, C, G, delay, Zo …)
- Change trace width
- Color mode
- Color by layer
- Color by net
- Control highlighting color
- Control background color
- Control lighting
- Interactive options
- Z stretch
- LMB pan, roller zoom
- Dynamic zoom or fast zoom'
- View cross section
- Hot keys (standard Ansoft ALT/SHIFT/LMB commands)
ANSYS ALinks for EDA uses the popular ANSYS SIwave user interface and includes many EDA-specific features.
Cadence Specific - ANSYS HFSS for ECAD
ANSYS HFSS for ECAD is a new paradigm for RF, SI and digital engineers. This technology enables users of Cadence software to set up ready-to-solve chip, package or PCB simulations directly from the Allegro Package Designer, Allegro PCB Designer, SiP Digital Layout, or Virtuoso Analog Design Environment for analysis in HFSS. All the necessary HFSS setup steps (geometry and net selection, material properties, excitations and boundary conditions) are completed in Cadence software and transferred to HFSS for solving the electromagnetic field and S-parameters via a single click. Users never leave the Cadence interface.
Cadence users have a choice between the automated ANSYS HFSS Solver on Demand or the traditional ALinks design flow. This traditional design flow enables a model created in Cadence to be imported to ANSYS DesignerSI or ANSYS DesignerRF where it can easily be modified in the Designer layout tool; it allows Cadence users the opportunity to take full advantage of additional capabilities including parametric sweeps, optimization and Full-Wave SPICE for full-wave, high-bandwidth SPICE model generation.
Easy Import and Edit of ECAD Geometry
- Generates 3-D solid models of selected traces, planes and vias
- Edit stackup properties, such as individual layer thickness, dielectric constant and conductivity
- Select nets for translation by net name(s), or point and click on specific traces or region of board
- Automatic defeaturing of selected nets to minimize model complexity and solution time
- Clip design to reduce translation size for field solvers
Cadence users can operate ANSYS HFSS directly from Allegro Package Designer, Allegro PCB Designer, SiP Digital Layout, or Virtuoso Analog Design Environment for highly accurate electromagnetic analysis of critical components.