ANSYS TPA Features
ANSYS TPA delivers advanced technology for automated parasitic extraction for IC packages.
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Automatic Adaptive Meshing 
A key benefit of TPA software is its automatic adaptive meshing techniques. Engineers are required to specify only geometry, material properties and the desired output. The meshing process uses a highly robust volumetric meshing technique and includes a multithreading capability that reduces the amount of memory used, thus speeding simulation time. This proven technology eliminates the complexity of building and refining a finite element mesh. It makes advanced numerical analysis practical for all levels of your organization.
Quasi-Static Field Solver
TPA contains advanced quasistatic 3-D electromagnetic field solvers based on the method of moments (MoM) accelerated by fast the multipole method (FMM). The results provided by these solvers include proximity and skin effect, dielectric and ohmic loss, and frequency dependencies. ANSYS TPA easily and quickly provides 3-D extraction of resistance (R), partial inductance (L), capacitance (C) and conductance (G).
Automated RLC Extraction
TPA fully characterizes an entire package structure and automatically produces lumped or distributed RLC (resistance, inductance and capacitance) values for any lead or coupled groups of leads in matrix or SPICE sub-circuit formats. These models can be generated directly from package layout tools — including Cadence, Mentor Graphics, Sigrity and Zuken — and exported into existing SPICE tools (SPICE/IBIS format) for subsequent timing analyses.
Layout Editor
ANSYS TPA includes an intuitive 2-D layout-based interface that allows engineers to create and modify package layouts and designs. TPA also has the ability to render geometry in 3-D with the integrated 3-D viewer.
The new 2-D layout editor and 3-D viewer enable:
- Creation of advanced wirebond or flip-chip designs from scratch or modification/correction of designs imported from third-party layout tools
- System-in-package (SiP) designs with multiple wirebond configurations including trace-to-trace, die-to-die and cascaded
- User-defined wirebond profiles expanding shapes from JEDEC 4- and 5-point to include arbitrary polylines
- Complex solder ball models that capture true shape and subsequent electrical performance of solder balls and flip-chip solder bumps
- Layer stack-up editing
- Via pad stack editing
- VB scripting support
- Performance of validation checks to verify setup, including detection of self-intersecting polygons; disjoint nets; overlapping (DC-shorted) nets, vias and bondwires; and illegal connections between bonding pads and bondwires
Equivalent Circuit Creation
You can use ANSYS TPA to create equivalent circuit models (SPICE subcircuits/ladder-type lumped models).
- Export for HSpice, PSpice, Spectre RF and other Berkeley-compatible SPICE tools
- Cadence DML, Synopsys SPEF and IBIS .pkg model
Design Flow Integration
ANSYS TPA integrates directly into electronic package layout tools, such as Cadence Advanced Package Designer (APD), Mentor Graphics Expedition, Sigrity UPD and Zuken CR-5000, to provide package engineers with a seamless design flow, automatically generating RLC models. The resulting electrical models can then be exported to and analyzed within ANSYS DesignerSI or other SPICE-compatible circuit tools.
High-Performance Computing
ANSYS TPA can leverage available computing power for fast turnaround of detailed parasitic extraction, even on large design layouts. HPC enables the ability to perform partitioning of the package over cores within a computer. Additionally, each solver (CG, ACRL and DCRL) employs shared-memory processing to speed solution times up to 100 times.
