ANSYS DesignerSI Features
ANSYS DesignerSI is an integrated circuit, system and EM field simulation tool that delivers technology for signal-integrity, power-integrity and EMI analysis.
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DesignerSI includes integrated schematic capture and layout tools, 2-D quasi-static field solver, circuit simulation (transient, fast convolution, statistical, and IBIS-AMI) and a design management front end for ANSYS best-in-class EM simulation products.
DesignerSI Circuit is targeted for engineers specifically interested in a transient, fast convolution, statistical and IBIS-AMI circuit simulation solution. DesignerSI Circuit includes the same functionality as DesignerSI except for the 2-D quasi-static field solver.
Solver on Demand technology enables DesignerSI to drive electromagnetic field solvers, HFSS and PlanarEM, as well as circuit simulation software, Nexxim and HSPICE, directly from its schematic and stack-up based layout interface. This intuitive interface is ideal for electrical CAD (ECAD) import, drawing, and parameterization of electromagnetic designs. An integrated stack-up design tool along with support for traditional ECAD primitives such as padstacks, traces, wire bonds, and solder balls propel a new state-of-the-art solution for digital and RF engineers. The ability to easily parameterize pre-and post-ECAD designs allows for a state-of-the-art EM solution where manufacturability and optimization can greatly reduce time to market.
ANSYS DesignerSI provides dynamic links to the widely used PCB and IC package design tools, ANSYS SIwave and ANSYS Q3D Extractor, to include their output within the design flow. Dynamic links differ from Solver on Demand technology in that output from these solvers can be linked to DesignerSI but the products cannot be driven directly from the DesignerSI interface as with the Solver on Demand technology.
Transient analysis from the ANSYS Nexxim circuit engine provides transistor level accuracy, robust convergence and large capacity. This allows engineers to create high-speed channel designs that include the driving circuitry as well as the channel. The driving circuitry can be transistor level, IBIS-based or ideal sources. When performing an analysis on these channels a user can select from a variety of analysis types.
- Transient analysis
- QuickEye and VerifEye analyses for fast eye generation in high-speed channel design, bathtub curves, jitter, and eye masks
- Monte Carlo analysis supporting Spectre® and HSPICE® functionality.
- DC analysis with automated convergence
- Dynamic links with ANSYS Q3D Extractor and ANSYS SIwave
- IBIS-AMI analysis and model support
DesignerSI enables engineers to determine if their DDR3 busses pass or fail the Jedec standard. This solution provides pass and fail criteria for key timing metrics such as DDR3 data setup and hold timings, derated analyses, bit to bit skew timing, overshoot, undershoot, etc. The virtual compliance solution automatically determines the pass and fail criteria for both the base and derated specifications on a per bit transition. Using DesignerSI dynamic links with SIwave, engineers can determine the effect that power and ground bounce have on the DDR3 timing measurements. Read and Write timing analyses can be performed within a single simulation environment that parameterizes all corner cases with automated reporting. This solution is scalable to any number of DDR3 bytes, ranks, DIMMs, and memory banks. Entire DDR3 systems can easily be solved starting with electromagnetic extraction using ANSYS electromagnetic field solver technologies to the pass/fail timing analyses with automated reporting. In addition to eye diagrams that display setup and hold timings engineers can look at flight time calculations, TDR plots, and automated .csv reports that show pass/fail for the DDR3 memory solution. The report provides in depth analysis on a bit by bit basis to show exactly which data lines are failing and at which transitions. The DDR3 virtual compliance solution can be customized by the user to accommodate user defined slew rate tables and customized reports. This solution can be used to create design kits for any bus that requires virtual compliance allowing it to extend to HDMI, USB, PCIe, GDDR, LPDDR and FibreChannel.
ANSYS DesignerSI offers several types of statistical and convolution analysis types that can rapidly and easily provide channel metrics such as BER, eye patterns etc.
VerifEye is a methodology for eye analysis of serial links using statistical methods that maintains accuracy while offering major reductions in run time compared to conventional transient methods. This statistical analysis tool represents the most practical means to test for the low bit-error rates needed by today's multi-Gb/s channel designers.
QuickEye is a fast convolution analysis that simulates millions of user-defined bits in a matter of seconds using linear superposition. Using the peak distortion analysis option QuickEye automatically determines the worst-case bit pattern for the design engineer by identifying the channel-specific bit pattern that causes maximum channel degradation.
IBIS-AMI is a fast analysis similar to the QuickEye or VerifEye analysis that allows you to incorporate channel equalization along with compiled vendor libraries. As with VerifEye and QuickEye, IBIS-AMI (advanced model interconnect) simulations include transmit jitter, receiver jitter and DCD. IBIS-AMI analysis supports GPU to speed the analysis.
DesignerSI includes a transmission line tool that enable engineers to quickly synthesize or analyze transmission lines. Features include
- Quasi-static 2-D electromagnetic field analysis
- RLGC parameters for transmission lines
- Characteristic impedance (Z0) matrices
- Propagation speed, delay, attenuation
- Differential and common-mode parameters
- Near- and far-end crosstalk coefficients
- Surface roughness modeling
- Equivalent circuit models creation
- Full wave (broadband), lumped model
- HSPICE, HSPICE W Element
- SPICE, Simplorer sml, Cadence DML
- Pspice, Spectre, Intel LCF, IBIS ICM
DesignerSI Network Data Explorer provides quick and easy analysis of S-, Y- and Z-parameters. This includes passivity checking and mixed-mode analyses. The data may be viewed in Re/Im, Mag/Phase, and dB/Phase. In addition, a colored map of all ports represents the average magnitude/phase over all frequencies or at a particular frequency point. Multiple Touchstone® files can be viewed simultaneously while cell filtering allows users to quickly analyze insertion and return loss. Furthermore, parametric design variations from ANSYS HFSS and ANSYS PlanarEM can be plotted simultaneously using the neutral model format (.anf).
ANSYS DesignerSI product suites are comprised of flexible, easy-to-use schematic capture, layout editing and sophisticated data visualization tools that are powered by the Nexxim high-capacity circuit engine. The powerful design management features allow DesignerSI to manage various solver technologies and import ECAD data from popular layout tools such as Cadence®, Mentor Graphics®, Zuken™ and Altium® along with ODB++ manufacturing databases. These features allow users to combine S-parameters, W-elements, HSPICE®, Spectre® and IBIS models directly as schematic components allowing them to seamlessly integrate with behavioral, circuit and GHz-accurate interconnect models in a unified schematic desktop.
DesignerSI transient circuit simulator advantages in speed and capacity are enhanced with enforcement of passivity and causality to accurately model and simulate physical behavior in the time domain, such as that of complex interconnects in signal integrity applications.
- Fully scripted design rule checking
- Highly customizable post-processing of results
- Transient and spectral plots
- Eye diagrams with characteristic measurements
- Bit error rate curves and contours
- 3-D swept parametric reports
- Statistical eye diagrams
- Design optimization, tuning, and swept parameter
- Statistical, sensitivity and yield analyses
- ANSYS DesignXplorer integration
- Transmission line calculator utility
- Network data explorer
- I/O Setup wizard
- Netlist encryption to protect IP
- Library development/ management UI with P-cell editor
- Component de-embedding
- Calibration wizard
- SPICE macro-cell netlist import wizard
- IBIS model import wizard
- Model Import wizards
DesignerSI supports a wide range of models for use in SI/PI simulations.
- Native HSPICE® and Spectre® model support
- CMOS, BiCMOS, SiGe and GaAs foundry libraries.
- Automated port reduction of Touchstone® files
- Behavioral and electrical models
- Verilog-A support
- Touchstone 2.0 support
- Native IBIS 5.0 support
- MOSFETs (BSIM4, HiSim, BSIMSOI, PSP, MET, etc.)
- BJTs (HiCUM, VBIC, HBT, Mextram, Modella, etc.)
- Diodes (SPICE, PIN, Microwave, JUNCAP, etc.)
- JFETs/MOSFETs (Statz, TOM3, Materka, EEHEMT, Parker-Skellern, Angelov, Curtice, etc.)
- Equalization: FFE, DFE, CTLE
- Independent and controlled sources
- Filters (Bessel, Butterworth, Elliptic, etc.)
- MOSFETs (BSIM4, HiSim, BSIMSOI, PSP, MET, etc.)
- SPICE import with encryption and IP protection
- Broadband interconnects: Macro-models (.sss), S- and W-elements
- Distributed transmission-line models and discontinuity models for:
- Microstrip and stripline
- Suspended stripline and offset stripline
- Coplanar and grounded coplanar waveguide
- Slotline and coaxial cable
- Multi-coupled transmission lines for arbitrary multi-level stack-up configurations
- Matlab support